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| SL4043B Quad 3-State R/S Latch High-Voltage Silicon-Gate CMOS The SL4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4043BN Plastic SL4043BD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs S X L L H PIN 13 = NO CONNECTION PIN 16=VCC PIN 8= GND H R X L H L H OE L H H H H Outputs Q High Impedance No change L H H X = don't care SLS System Logic Semiconductor SL4043B MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL4043B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Three State Leakage Current Test Conditions VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 18 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.4 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 12.0 Unit V VIL V VOH V VOL VIN=GND or VCC V IIN IOZ VIN= GND or VCC Output in High-Impedance State VIN= GND or VCC VOUT= GND or VCC VIN= GND or VCC A A ICC Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 1 2 4 20 0.64 1.6 4.2 -2 -0.64 -1.6 -4.2 1 2 4 20 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 30 60 120 600 0.36 0.9 2.4 A IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V mA -1.15 -0.36 -0.9 -2.4 SLS System Logic Semiconductor SL4043B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input t r=t f=20 ns) VCC Symbol tPHL, t PLH Parameter Maximum Propagation Delay, SET or RESET to Q (Figure 1) Maximum Propagation Delay, Output Enable to Q (Figures 2,4) Maximum Propagation Delay, Output Enable to Q (Figures 2,4) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 300 140 100 230 110 80 180 100 70 200 100 80 25C 300 140 100 230 110 80 180 100 70 200 100 80 7.5 125C 600 280 200 460 220 160 360 200 140 400 200 160 Unit ns tPHZ, t PZH ns tPLZ, t PZL ns tTHL, t TLH ns CIN pF TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input t r=t f=20 ns) VCC Symbol tw Parameter Minimum Pulse Width, SET or RESET (Figure 3) V 5.0 10 15 Guaranteed Limit -55C 160 80 40 25C 160 80 40 125C 320 160 80 Unit ns Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL4043B Figure 3. Switching Waveforms SLS System Logic Semiconductor SL4043B TEST tPHZ tPLZ tPZH tPZL IN VCC GND VCC GND IN GND VCC GND VCC A GND VCC GND VCC Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM ( 1/4 of the Device) SLS System Logic Semiconductor |
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